When is it necessary to use the reset of your devices?

When is it necessary to use the reset of your devices?

ADC TS8388B and TS83102G0

The Data Ready Asynchronous Reset (DRRB) is provided with our devices to ensure that the first digitized data (after Reset) is detected by the third rising edge of the Data Ready signal.

This functionality is especially useful when the first acquisition performed by the loading system of the ADC depends on the nature of the Data Ready Signal edge.

The Data Ready Asynchronous Reset pulse must last at least 1ns. When this reset is applied, the clock must be held at either low or high level.

Note: This Reset is not used to start the device.

DMUX TS81102G0

There are two Resets that are available with our DMUX device.

- The Synchronous Reset is used to ensure a cyclic synchronization of the port selection. It permits to minimize the loss of data due to internal de-synchronization. The Synchronous Reset signal must be cyclic because each of its rising edges involves a port selection restart on Port A. Its frequency must be in the form Fs/8n for 1:8 ratio and Fs/4n for 1:4 ratio (n = 1, 2,…).

During a Synchronous Reset, the clock is not stopped.

Note: This Reset is not used to start the device.

- The Asynchronous Reset is required to start the DMUX. It can only work if the clock is already running. When it is active (high level), it freezes all the outputs (output clock and data) and after it is applied, the first data at the output of the DMUX is available on port A, after a slight delay (next first clock rising edge + Pipeline Delay + Outputs Propagation delay).

Note: When the DMUX is used with e2v-Grenoble ADCs, the reset sequence for both devices is described thereafter.

- Apply an asynchronous reset on the ADC via the DRRB signal if applicable;

- Wait for the ADC Output Data Ready signal, which goes to the DMUX input clock, to start;

- Apply an Asynchronous Reset on the DMUX.

After a slight delay, the data should be available at the outputs of the DMUX.