Interfacing the Dual 8-bit 1Gsps ADC

How to reduce the data output speed of the Dual 8-bit 1Gsps ADC by 1:4 or 1:8 ratio?

It is possible to use the TS81102G0 8-/10-bit 1:4/8 DMUX together with the AT84AD001B Dual 8-bit 1GSps ADC in order to reduce the ADC data output speed by a factor of 4 or 8 as needed by the system requirements.

Timing considerations
In order to achieve a 1:4 or a 1:8 ratio at the (ADC + DMUX) system output, we recommend to use the dual 8-bit ADC in 1:1 DMUX mode with 2 DMUXes in 1:4 or 1:8 ratio.

Note:
Another possibility would be to use the ADC in 1:2 DMUX mode but then, 2 DMUXes (output on 2 x 2 ports in 1:2 DMUX) would be needed to demultiplex the ADC data for 1 channel (4 DMUXes if I and Q channels are used).

The ADC-DMUX settings are consequently:
Dual ADC in 1:1 DMUX mode;
DMUX in 8-bit, 1:4 or 1:8 ratio, DR/2 modes.

Electrical considerations:
1. The dual 8-bit 1Gsps output buffers are LVDS buffers with the following characteristics:
VOL min = 0.925V VOH min = 1.3V
VOL typ = 1.1V VOH typ = 1.4V
VOL max = 1.2V VOH max = 1.475V
These buffers have to be 100 ohm differentially terminated.
2. The DMUX input buffers are specified to only accept negative levels (ECL). However, they can also accept up to +0.6V max positive level.
To interface the dual 8-bit ADC with this DMUX, the user needs to AC couple each data output of the ADC with a 100nF capacitor (for information only) to get rid of the DC offset of the output data from the ADC.