The dynamic Built-In-Test allows you to test the output bits of the ADC
at speeds up to 500 MHz for the 500 Msps ADC version and 750 MHz
for the 1 Gsps ADC version without applying an input signal to the ADC.
In 1:1 DMUX mode, a decreasing ramp of all bits is output on port A.
The same codes appear on both channel I and Q providing the same
clock is sent to both channels. Each edge of the clock (rising and falling)
corresponds to a valid data.
Port A: decreasing ramp
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In 1:2 DMUX, Fs/2 mode, a decreasing ramp of all bits is output on port
A while an increasing ramp is output on port B. The same codes appear
on both channel I and Q (IA = QA and IB = QB) providing the same clock
is sent to both channels. Each edge of the clock (rising and falling)
corresponds to a valid data.
Port B : increasing ramp
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In 1:2 DMUX, Fs/4 mode, a decreasing ramp is output on port A while
an increasing ramp is output on port B. Not all codes are output:
only even or only odd codes.
Code (N+1) = Code (N) + 2 on port B
Code (N+1) = Code (N) – 2 on port A
The same codes appear on both channel I and Q (IA = QA and IB = QB)
providing the same clock is sent to both channels.
Each edge of the clock (rising and falling) corresponds to a valid data.
Port A: decreasing ramp with only even codes
.jpg)
Port A: decreasing ramp with only odd codes
.jpg)
Port B: increasing ramp with only even codes
.jpg)
Port B : increasing ramp with only odd codes
.JPG)
