AT84AD001 Dual 8-bit 1Gsps Timings at power up

How does the AT84AD001 dual 8-bit 1Gsps ADC behave at power up?

After power up, and prior to the application of the input clocks into the device, the data ready output clocks toggle between LVDS high and low levels. As soon as an input clock is applied the Data ready signals start properly but it is difficult to know how they start in practice (high or low level).
The only way to know exactly the behavior of the data ready clocks is to assert the data ready reset right after power up and until the input clock(s) has reached its steady state. The reset can then be released and the data ready will go high (low during reset).

This is all depicted by the following timing diagram :