AT84AD001 Dual 8-bit 1Gsps ADC Input Clock implementation in Single-ended mode

What is the recommended termination scheme for the
input clock of the AT84AD001 Dual 8-bit 1Gsps
ADC in single-ended mode?

It is recommended to AC couple both CLK and CLKB signals in
order to remove the VCCA/2 internal bias and to terminate
the CLKB signal with a 50 Ohm resistor to ground,
as illustrated in the figure below.